Many of today's handheld devices make use of wireless “connections” for telephony, digital data transfer, geographical positioning, and the like. Despite differences in frequency spectra, modulation methods, and spectral power densities, the wireless connectivity standards use synchronized data packets to transmit and receive data.
In general, all of these wireless-connectivity capabilities (e.g., WiFi, WiMAX, Bluetooth, etc.) are defined by industry-approved standards (e.g., IEEE 802.11 and IEEE 802.16) which specify the parameters and limits to which devices having those connectivity capabilities must adhere.
At any point along the device-development continuum, it may be necessary to test and verify that a device is operating within its standards' specifications. Most such devices are transceivers, that is, they transmit and receive wireless RF signals. Specialized systems designed for testing such devices typically contain subsystems designed to receive and analyze device-transmitted signals, and to send signals that subscribe to industry-approved standards so as to determine whether a device is receiving and processing the wireless signals in accordance with its standard.
Increasingly, wireless devices are using embedded control subsystems to control the operations of a variety of wireless capabilities, such as 3G cellular, IEEE 802.11x, Bluetooth, and the like. Such designs may limit the test-control interface options and force control to be accomplished through an embedded controller rather than directly with a specific subsystem. In addition, there is continuous pressure to reduce both the cost of manufacturing such devices, and for testing their operation during manufacturing. Any innovation that can reduce the time required for testing such devices, without compromising the integrity of the testing, will result in lower test costs.
FIG. 1 depicts a prior testing setup 100 which may generally comprise a tester 104 with vector-signal analysis (VSA) and vector-signal generation (VSG) functionality, a device under test (DUT) 101 with stored predefined test sequences 102, and a PC controller 106 for controlling the tester. A bidirectional communications interface 103 supports communications between the DUT 101 and tester 104. Likewise, a bidirectional communications interface 105 supports communications between the PC controller 106 and tester 104. The bidirectional communications interfaces 103, 105 may be conductive or wireless (e.g., RF, IR, etc.) interfaces. The DUT 101, as shown, is capable of storing a predefined test sequence 102 of which both the DUT 101 and tester 104 are “aware.” By this configuration, one can reduce the number of non-test-related communications interactions between the DUT and tester.
Referring to FIG. 2, the test system of FIG. 1 can be used to implement a loop-back test whereby packets 203, 204, 205 sent by the tester 202 are received by the DUT 201. In turn, the DUT 201 will send the packet payloads received embedded as new packets 206, 207, 208, respectively, back to tester 202. Thus, if tester 202 sends three packets using three time slots, the DUT 201 will loop back three packets using three time slots. The total time, in this case, would be six time slots. While proven useful, additional time slots would be required for extensive testing sequences and for multiple devices.
Other systems and methods have been employed in an attempt to test disclosed systems in an efficient manner. Referring to FIG. 3, the same apparatus of FIG. 2 is now used with the addition of a multiport interface 310 between the tester 305 and multiple DUTs 301-304 under test. The multiport interface or splitter interface 310 is employed whereby a sequence of packets 306, 307, 308 may be replicated in parallel. In this exemplary setup, the multiport interface 310 is a four-port splitter (one in/four out) configured for four DUTs to be simultaneously tested. The tester 305, using a single VSG, sends a sequence of packets 306, 307, 308, which are replicated using the circuitry of the splitter 310 as is well known in the art. The multiport interface 310 can be part of (e.g., internal to) and controlled by the host controller of tester 305, or can be separate from (e.g., external to) tester 305 and controlled by the host controller of tester 305 via a control interface (not shown). Each packet sent by the VSG results in four copies of the data packets 306, 307, 308 sent to each of the DUTs 301, 302, 303, 304, as shown. As a result, the three time slots used for sending the three VSG packets results in three sets of four copies of the packets being received by the four DUTs 301, 302, 303, 304. Consequently, the per-DUT test time required for receiving the aforementioned three packets is one-fourth that of the single-DUT test case.
Still, there is continuous pressure to reduce the cost of both manufacturing such devices and for testing their operation during manufacturing. Any innovation that can reduce the time required for testing such devices, without compromising the integrity of the testing, will be ultimately expected to lower test costs as a result. Accordingly, a need exists for innovative systems and techniques that address, and can obtain, these goals.